1. Field of the Invention
The present invention relates to digital-to-analog converters, and more particularly to pulse width modulation digital-to-analog converters.
2. Description of Related Art
Digital-to-analog converters (DACs) provide the interface between digital logic and the external analog world. One such application of digital-to-analog converters is the interface in hard disk drives between digital servo control circuits and analog voice coil motor control signals. These analog control signals control the radial position of the read/write heads on the disks. Data is stored on disks in concentric tracks. The voice coil motor moves the heads to tracks to read and write data. To increase storage capacity, track widths have been greatly reduced. The narrower tracks require greater DAC resolution to ensure that the heads are properly positioned over the tracks for data read/write operations.
DAC performance requirements are primarily based on resolution, speed and linearity. Linearity is a measure of a DAC""s accuracy. One component of linearity is the extent to which the DAC output from the minimum value to the maximum value adheres to a straight line between those endpoints. A second component of linearity is the linearity between code transitions. A DAC is said to be monotonic if each increase in input value results in a corresponding change in the DAC output value. Linearity and monotonicity are critical in demanding applications such as disk drive servo control.
Pulse width modulation (PWM) DACs are often used where monotonicity is a critical requirement. In PWM DACs, n bits are provided as an input code to a pulse generator. The pulse generator also has a system clock input signal. The system clock frequency defines the minimum resolution of the DAC. The number of bits in the input code and the frequency of the clock determine the conversion period of the DAC. For example, typically an input code with only the least significant bit set corresponds to an output of one pulse for the DAC conversion period, and an input code with all of the bits set corresponds to an output of the maximum number of pulses in the conversion. PWM DACs provide highly reliable monotonicity because for a given finite resolution an additional pulse will increase the output value. To increase the resolution of a PWM DAC, the number of bits in the input code can be increased. However, to cover the full dynamic range, the conversion period includes one pulse period per input code bit. Therefore, for a given clock frequency, an increase in the resolution of a PWM DAC requires an increase in the conversion period. Alternatively, if a higher system clock frequency is used, a greater number of pulse periods could be included in a given conversion period. However, the maximum clock frequency that can be used is limited by semiconductor process technology and cost constraints. As a result in high speed, high resolution PWM DAC applications, the PWM DAC can limit the speed and accuracy of the system.
In contrast to PWM DACs, a flash DAC produces an analog value corresponding to a digital input immediately upon receipt of the digital input. The output then stays at a constant value until the digital input is changed.
One conventional type of flash DAC uses resistive ladder networks or R-2R networks, in which a digital word is used to control the switching of various points in resistive divider networks to generate the correct output voltage. One drawback with this type of structure is that the precision of the resistors effects the output, and therefore there is often a trimming step involved. The accuracy of trimming processes can create monotonicity limitations for high resolution implementations. Increasing the resolution of this type of flash DAC generally increases the cost due to larger circuit size and more demanding trimming requirements.
Another conventional type of flash DAC uses current sources of different ratios to generate the output voltages. In these DACs, limitations on transistor matching and ratios are limiting factors of the DAC accuracy and monotonicity for high resolution implementations.
In view of the foregoing problems and limitations, there is a need for improved PWM DACs.
An object of the present invention is therefore to improve the speed and resolution of pulse width modulation (PWM) digital-to-analog converters (DACs). The present invention provides a variable pulse pulse width modulation digital-to-analog converter comprising: an input code register to store a digital input code to be converted; a PWM decoder, coupled to the input code register, to convert the input code to a series of pulses; an output driver circuit coupled to the PWM decoder, wherein the output driver circuit generates an output signal comprising pulses of a high logic level and pulses of an intermediate logic level; and a filter to integrate the pulses to generate an analog output value corresponding to the digital input code. In one embodiment, the output stage comprises an active tri-state driver, a multiplexer and at least two output reference voltage sources.
In operation, a digital input code to be converted is loaded into the n-bit DAC register. When the Load signal input to the PWM decoder is asserted, the input code is loaded into n-bit PWM decoder. The PWM decoder converts the input code into a pulse train and corresponding Vref Select signals. The reference voltage sources define the amplitude of the pulse output of the multilevel active tri-state driver. Vref Select signals determine which of the reference voltage sources is coupled to the tri-state driver for each pulse the tri-state driver outputs to the filter. The Vref Select signal is comprised of a sufficient number of bit lines to enable each of the voltage references to be uniquely identified. Using a plurality of different amplitude pulse levels enables PWM DACs according to the present invention to provide greater resolution than conventional PWM DACs for a given clock frequency and conversion period.
In a further embodiment a plurality of output pulses are generated for each digital input code period. Providing more than one pulse per input period increases the resolution of the PWM DAC without increasing the frequency of the input data .